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general description the max5038/max5041 dual-phase, pwm controllers provide high-output-current capability in a compact package with a minimum number of external compo- nents. the max5038/max5041 utilize a dual-phase, average current-mode control that enables optimal use of low r ds(on) mosfets, eliminating the need for exter- nal heatsinks even when delivering high output currents. differential sensing enables accurate control of the out- put voltage, while adaptive voltage positioning provides optimum transient response. an internal regulator enables operation with input voltage ranges of +4.75v to +5.5v or +8v to +28v. the high switching frequency, up to 500khz per phase, and dual-phase operation allow the use of low-output inductor values and input capacitor values. this accommodates the use of pc board- embedded planar magnetics achieving superior reliabili- ty, current sharing, thermal management, compact size, and low system cost. the max5038/max5041 also feature a clock input (clkin) for synchronization to an external clock, and a clock output (clkout) with programmable phase delay (relative to clkin) for paralleling multiple phases. the max5038 offers a variety of factory-trimmed preset output voltages (see selector guide ) and the max5041 offers an adjustable output voltage from +1.0v to +3.3v. the max5038/max5041 operate over the extended industrial temperature range (-40? to +85?) and are available in a 28-pin ssop package. refer to the max5037 data sheet for a vrm 9.0-compatible, vid- controlled output voltage controller in a 44-pin mqfp or qfn package. applications servers and workstations point-of-load high-current/high-density telecom dc-dc regulators networking systems large-memory arrays raid systems high-end desktop computers features ? +4.75v to +5.5v or +8v to +28v input voltage range ? up to 60a output current ? internal voltage regulator for a +12v or +24v power bus ? true differential remote output sensing ? two out-of-phase controllers reduce input capacitance requirement and distribute power dissipation ? average current-mode control superior current sharing between individual phases and paralleled modules accurate current limit eliminates mosfet and inductor derating ? integrated 4a gate drivers ? selectable fixed frequency 250khz or 500khz per phase (up to 1mhz for 2 phases) ? fixed (max5038) or adjustable (max5041) output voltages ? 0.5% accurate reference (max5041b) ? external frequency synchronization from 125khz to 600khz ? internal pll with clock output for paralleling multiple dc-dc converters ? thermal protection ? 28-pin ssop package max5038/max5041 dual-phase, parallelable, average current-mode controllers ________________________________________________________________ maxim integrated products 1 19-2514; rev 3; 8/04 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. ordering information part temp range pin- package output voltage max5038 eai12 -40? to +85? 28 ssop fixed +1.2v max5038eai15 -40? to +85? 28 ssop fixed +1.5v max5038eai18 -40? to +85? 28 ssop fixed +1.8v max5038eai25 -40? to +85? 28 ssop fixed +2.5v max5038eai33 -40? to +85? 28 ssop fixed +3.3v max5041 eai -40? to +85? 28 ssop adj +1.0v to +3.3v MAX5041BEAI -40? to +85? 28 ssop adj +1.0v to +3.3v pin configuration appears at end of data sheet.
max5038/max5041 dual-phase, parallelable, average current-mode controllers 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v cc = +5v, circuit of figure 1, t a = -40? to +85?, unless otherwise noted. typical specifications are at t a = +25?.) (note 1) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. in to sgnd.............................................................-0.3v to +30v bst_ to sgnd.?0.3v to +35v dh_ to lx_ ................................-0.3v to [(v bst _ - v lx _) + 0.3v] dl_ to pgnd ..............................................-0.3v to (v cc + 0.3v) bst_ to lx_ ..............................................................-0.3v to +6v v cc to sgnd............................................................-0.3v to +6v v cc to pgnd............................................................-0.3v to +6v sgnd to pgnd .....................................................-0.3v to +0.3v all other pins to sgnd...............................-0.3v to (v cc + 0.3v) continuous power dissipation (t a = +70?) 28-pin ssop (derate 9.5mw/? above +70?) ............762mw operating temperature range ...........................-40? to +85? maximum junction temperature .....................................+150? storage temperature range .............................-60? to +150? lead temperature (soldering, 10s) .................................+300? parameter symbol conditions min typ max units system specifications 828 input voltage range v in short in and v cc together for +5v input operation 4.75 5.5 v quiescent supply current i q en = v cc or sgnd 4 10 ma efficiency i load = 52a (26a per phase) 90 % output voltage max5038 only, no load -0.8 +0.8 nominal output voltage accuracy max5038 only, no load, v in = v cc = +4.75v to +5.5v or v in = +8v to +28v (note 2) -1 +1 % max5041 only, no load 0.992 1.008 max5041 only, no load, v in = v cc = +4.75v to +5.5v or v in = +8v to +28v 0.990 1.010 max5041b only, no load 0.995 1.005 sense+ to sense- voltage accuracy max5041b only, no load, v in = +8v to +28v 0.995 1.005 v startup/internal regulator v cc undervoltage lockout uvlo v cc falling 4.0 4.15 4.5 v v cc undervoltage lockout hysteresis 200 mv v cc output accuracy v in = +8v to +28v, i source = 0 to 80ma 4.85 5.1 5.30 v mosfet drivers output driver impedance r on low or high output 1 3 ? output driver source/sink current i dh _, i dl _ 4a non-overlap time t no c dh _ /dl _ = 5nf 60 ns
max5038/max5041 dual-phase, parallelable, average current-mode controllers _______________________________________________________________________________________ 3 electrical characteristics (continued) (v cc = +5v, circuit of figure 1, t a = -40? to +85?, unless otherwise noted. typical specifications are at t a = +25?.) (note 1) parameter symbol conditions min typ max units oscillator and pll clkin = sgnd 238 250 262 switching frequency f sw clkin = v cc 475 500 525 khz pll lock range f pll 125 600 khz pll locking time t pll 200 ? phase = v cc 115 120 125 phase = unconnected 85 90 95 clkout phase shift (at f sw = 125khz) = + = ( ) = ( ) current limit average current-limit threshold v cl csp_ to csn_ 45 48 51 mv cycle-by-cycle current limit v clpk csp_ to csn_ (note 3) 90 112 130 mv cycle-by-cycle overload response time t r v csp _ to v csn _ = +150mv 260 ns current-sense amplifier csp_ to csn_ input resistance r cs _4k ? common-mode range v cmr ( cs ) -0.3 +3.6 v input offset voltage v os ( cs ) -1 +1 mv amplifier gain a v(cs) 18 v/v 3db bandwidth f 3db 4 mhz current-error amplifier (transconductance amplifier) transconductance gm ca 550 ? open-loop gain a vol ( ce ) no load 50 db differential voltage amplifier (diff) common-mode voltage range v cmr ( diff ) -0.3 +1.0 v diff output voltage v cm v sense+ = v sense- = 0 0.6 v input offset voltage v os ( diff ) -1 +1 mv max5038/max5041 (+1.2v, +1.5v, +1.8v output versions) 0.997 1 1.003 amplifier gain a v ( diff ) max5038 (+2.5v and +3.3v output versions) 0.495 0.5 0.505 v/v
max5038/max5041 dual-phase, parallelable, average current-mode controllers 4 _______________________________________________________________________________________ electrical characteristics (continued) (v cc = +5v, circuit of figure 1, t a = -40? to +85?, unless otherwise noted. typical specifications are at t a = +25?.) (note 1) parameter symbol conditions min typ max units 3db bandwidth f 3db c diff = 20pf 3 mhz minimum output current drive i out ( diff ) 1.0 ma sense+ to sense- input resistance r vs _50 100 k ? voltage-error amplifier (eaout) open-loop gain a vol ( ea ) 70 db unity-gain bandwidth f ugea 3mhz ean input bias current i b(ea) v ean = +2.0v -100 +100 na error-amplifier output clamping voltage v clamp ( ea ) with respect to v cm 810 918 mv thermal shutdown thermal shutdown t shdn 150 ? thermal-shutdown hysteresis 8c en input en input low voltage v enl 1v en input high voltage v enh 3v en pullup current i en 4.5 5 5.5 ? note 1: specifications from -40? to 0? are guaranteed by characterization but not production tested. note 2: guaranteed by design. not production tested. note 3: see peak-current comparator section.
max5038/max5041 dual-phase, parallelable, average current-mode controllers _______________________________________________________________________________________ 5 efficiency vs. output current and internal oscillator frequency max5038/41 toc01 i out (a) (%) 48 44 40 36 32 28 24 20 16 12 8 4 50 60 70 80 90 100 40 052 f = 500khz f = 250khz v in = +5v v out = +1.8v efficiency vs. output current and input voltage max5038/41 toc02 i out (a) (%) 48 44 40 36 32 28 24 20 16 12 8 4 50 40 30 20 10 60 70 80 90 100 0 052 v in = +12v v in = +5v v out = +1.8v f sw = 250khz efficiency vs. output current max5038/41 toc03 i out (a) (%) 48 44 40 36 32 28 24 20 16 12 8 4 50 40 30 20 10 60 70 80 90 100 0 052 v in = +24v v out = +1.8v f sw = 125khz efficiency vs. output current and output voltage max5038/41 toc04 i out (a) (%) 48 44 40 36 32 28 24 20 16 12 8 4 50 40 30 20 10 60 70 80 90 100 0 052 v out = +1.1v v out = +1.5v v out = +1.8v v in = +12v f sw = 250khz efficiency vs. output current and output voltage max5038/41 toc05 i out (a) (%) 48 44 40 36 32 28 24 20 16 12 8 4 50 40 30 20 10 60 70 80 90 100 0 052 v out = +1.1v v out = +1.5v v out = +1.8v v in = +5v f sw = 500khz supply current vs. frequency and input voltage max5038/41 toc06 frequency (khz) i cc (ma) 550 500 400 450 200 250 300 350 150 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 10.5 11.0 11.5 12.0 6.0 100 600 v in = +24v v in = +12v v in = +5v externalclock no driver load supply current vs. temperature and frequency max5038/41 toc07 temperature ( c) i cc (ma) 60 35 10 -15 10 20 30 40 50 60 70 80 90 100 0 -40 85 250khz 125khz v in = +12v c dl_ = 22nf c dh_ = 8.2nf supply current vs. temperature and frequency max5038/41 toc08 temperature ( c) i cc (ma) 60 35 10 -15 50 75 100 125 150 175 25 -40 85 600khz 500khz v in = +5v c dl_ = 22nf c dh_ = 8.2nf supply current vs. load capacitance per driver max5038/41 toc09 c driver (nf) i cc (ma) 13 11 7 9 5 3 10 20 30 40 50 60 70 80 90 100 0 115 v in = +12v f sw = 250khz typical operating characteristics (circuit of figure 1. t a = +25?, unless otherwise noted.)
max5038/max5041 dual-phase, parallelable, average current-mode controllers 6 _______________________________________________________________________________________ typical operating characteristics (continued) (circuit of figure 1, t a = +25?, unless otherwise noted.) current-sense threshold vs. output voltage max5038/41 toc10 v out (v) (v csp_ - v csn_ ) (mv) 1.7 1.6 1.4 1.5 1.2 1.3 1.1 46 47 48 49 50 51 52 53 54 55 45 1.0 1.8 phase 2 phase 1 output voltage vs. output current and error amp gain (r f / r in ) max5038/41 toc11 i load (a) v out (v) 50 45 40 35 30 25 20 15 10 5 1.65 1.70 1.75 1.80 1.85 1.60 055 v in = +12v v out = +1.8v r f / r in = 15 r f / r in = 12.5 r f / r in = 10 r f / r in = 7.5 differential amplifier bandwidth max5038/41 toc12 frequency (mhz) gain (v/v) phase (deg) 1 0.1 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0 0.01 10 -225 -270 -180 -135 -90 -45 0 45 90 phase gain diff output error vs. sense+ to sense- voltage max5038/41 toc13 ? v sense (v) error (%) 1.9 1.8 1.1 1.2 1.3 1.5 1.6 1.4 1.7 0.025 0.050 0.075 0.100 0.125 0.150 0.175 0.200 0 1.0 2.0 v in = +12v no driver v cc load regulation vs. input voltage max5038/41 toc14 i cc (ma) v cc (v) 135 120 15 30 45 75 90 60 105 4.85 4.90 4.95 5.00 5.05 5.10 5.15 5.20 4.80 0 150 v in = +24v v in = +12v v in = +8v dc load v cc line regulation max5038/41 toc15 v in (v) v cc (v) 26 24 20 22 12 14 16 18 10 4.80 4.85 4.90 4.95 5.00 5.05 5.10 5.15 5.20 5.25 4.75 828 i cc = 0 i cc = 40ma v cc line regulation max5038/41 toc16 v in (v) v cc (v) 13.0 12.0 9.0 10.0 11.0 4.80 4.85 4.90 4.95 5.00 5.05 5.10 5.15 5.20 5.25 4.75 8.0 i cc = 80ma driver rise time vs. driver load capacitance max5038/41 toc17 c driver (nf) t r (ns) 31 26 16 21 11 6 10 20 30 40 50 60 70 80 90 100 110 120 0 136 dl_ dh_ v in = +12v f sw = 250khz driver fall time vs. driver load capacitance max5038/41 toc18 c driver (nf) t f (ns) 31 26 16 21 11 6 10 20 30 40 50 60 70 80 90 100 110 120 0 136 dl_ dh_ v in = +12v f sw = 250khz
max5038/max5041 dual-phase, parallelable, average current-mode controllers _______________________________________________________________________________________ 7 100ns/div high-side driver (dh_) sink and source current dh_ 1.6a/div max5038/41 toc19 v in = +12v c dh_ = 22nf 100ns/div low-side driver (dl_) sink and source current dl_ 1.6a/div max5038/41 toc20 v in = +12v c dl_ = 22nf 100 s/div pll locking time 250khz to 350khz and 350khz to 250khz clkout 5v/div max5038/41 toc21 pllcmp 200mv/div v in = +12v no load 350khz 250khz 0 100 s/div pll locking time 250khz to 500khz and 500khz to 250khz clkout 5v/div max5038/41 toc22 pllcmp 200mv/div 0 v in = +12v no load 500khz 250khz 100 s/div pll locking time 250khz to 150khz and 150khz to 250khz clkout 5v/div max5038/41 toc23 pllcmp 200mv/div 0 v in = +12v no load 250khz 150khz 40ns/div high-side driver (dh_) rise time max5038/41 toc24 v in = +12v c dh_ = 22nf dh_ 2v/div 40ns/div high-side driver (dh_) fall time max5038/41 toc25 dh_ 2v/div v in = +12v c dh_ = 22nf 40ns/div low-side driver (dl_) rise time max5038/41 toc26 dl_ 2v/div v in = +12v c dl_ = 22nf 40ns/div low-side driver (dl_) fall time max5038/41 toc27 dl_ 2v/div v in = +12v c dl_ = 22nf typical operating characteristics (continued) (circuit of figure 1, t a = +25?, unless otherwise noted.)
max5038/max5041 dual-phase, parallelable, average current-mode controllers 8 _______________________________________________________________________________________ typical operating characteristics (continued) (circuit of figure 1, t a = +25?, unless otherwise noted.) 500ns/div output ripple max5038/41 toc28 v out (ac-coupled) 10mv/div v in = +12v v out = +1.75v i out = 52a 2ms/div input startup response max5038/41 toc29 v in 5v/div v in = +12v v out = +1.75v i out = 52a v pgood 1v/div v out 1v/div 1ms/div enable startup response max5038/41 toc30 v en 2v/div v pgood 1v/div v out 1v/div v in = +12v v out = +1.75v i out = 52a 40 s/div load-transient response max5038/41 toc31 v in = +12v v out = +1.75v i step = 8a to 52a t rise = 1 s v out 50mv/div
max5038/max5041 dual-phase, parallelable, average current-mode controllers _______________________________________________________________________________________ 9 pin description pin name function 1, 13 csp2, csp1 current-sense differential amplifier positive input. senses the inductor current. the differential voltage between csp_ and csn_ is amplified internally by the current-sense amplifier gain of 18. 2, 14 csn2, csn1 current-sense differential amplifier negative input. senses the inductor current. 3 phase phase-shift setting input. connect phase to v cc for 120 , leave phase unconnected for 90 , or connect phase to sgnd for 60 of phase shift between the rising edges of clkout and clkin/dh1. 4 pllcmp external loop-compensation input. connect compensation network for the phase lock loop (see phase- locked loop section). 5, 7 clp2, clp1 current-error amplifier output. compensate the current loop by connecting an rc network to ground. 6 sgnd signal ground. ground connection for the internal control circuitry. 8 sense+ differential output voltage-sensing positive input. used to sense a remote load. connect sense+ to v out+ at the load. the max5038 regulates the difference between sense+ and sense- according to the factory preset output voltage. the max5041 regulates the sense+ to sense- difference to +1.0v. 9 sense- differential output voltage-sensing negative input. used to sense a remote load. connect sense- to v out- or pgnd at the load. 10 diff differential remote-sense amplifier output. diff is the output of a precision unity-gain amplifier. 11 ean voltage-error amplifier inverting input. receives the output of the differential remote-sense amplifier. referenced to sgnd. 12 eaout voltage-error amplifier output. connect to the external gain-setting feedback resistor. the external error amplifier gain-setting resistors determine the amount of adaptive voltage positioning 15 en output enable. a logic low shuts down the power drivers. en has an internal 5? pullup current. 16, 26 bst1, bst2 boost flying-capacitor connection. reservoir capacitor connection for the high-side fet driver supply. connect 0.47? ceramic capacitors between bst_ and lx_. 17, 25 dh1, dh2 high-side gate driver output. drives the gate of the high-side mosfet. 18, 24 lx1, lx2 inductor connection. source connection for the high-side mosfets. also serves as the return terminal for the high-side driver. 19, 23 dl1, dl2 low-side gate driver output. synchronous mosfet gate drivers for the two phases. 20 v cc internal +5v regulator output. v cc is derived internally from the in voltage. bypass to sgnd with 4.7? and 0.1? ceramic capacitors. 21 in supply voltage connection. connect in to v cc for a +5v system. connect the vrm input to in through an rc lowpass filter, a 2.2 ? resistor and a 0.1? ceramic capacitor. 22 pgnd power ground. connect pgnd, low-side synchronous mosfet? source, and v cc bypass capacitor returns together. 27 clkout oscillator output. clkout is phase-shifted from clkin by the amount specified by phase. use clkout to parallel additional max5038/max5041s. 28 clkin cmos logic clock input. drive the internal oscillator with a frequency range between 125khz and 600khz. the pwm frequency defaults to the internal oscillator if clkin is connected to v cc or sgnd. connect clkin to sgnd to set the internal oscillator to 250khz or connect to v cc to set the internal oscillator to 500khz. clkin has an internal 5? pulldown current.
max5038/max5041 dual-phase, parallelable, average current-mode controllers 10 ______________________________________________________________________________________ max5038 max5041 in en phase 1 csp1 drv_v cc ramp1 gm in clk clp1 csn1 shdn bst1 dl1 lx1 dh1 v cc to internal circuits csp1 csn1 clp1 phase 2 csp2 drv_v cc gm in clk clp2 csn2 shdn bst2 dl2 lx2 dh2 csp2 csn2 clp2 phase- locked loop ramp generator ramp2 clkin clkout pllcmp diff amp error amp sense- sense+ diff ean eaout pgnd pgnd pgnd sgnd v ref = v out for v out 1.8v (max5038) v ref = v out /2 for v out > 1.8v (max5038) v ref = +1.0v (max5041) +5v ldo regulator uvlo por temp sensor 0.6v functional diagram
max5038/max5041 dual-phase, parallelable, average current-mode controllers ______________________________________________________________________________________ 11 detailed description the max5038/max5041 (figures 1 and 2) average cur- rent-mode pwm controllers drive two out-of-phase buck converter channels. average current-mode con- trol improves current sharing between the channels while minimizing component derating and size. parallel multiple max5038/max5041 regulators to increase the output current capacity. for maximum ripple rejection at the input, set the phase shift between phases to 90 for two paralleled converters, or 60 for three paralleled converters. paralleling the max5038/max5041s improves design flexibility in applications requiring upgrades (higher load). clkin pllcmp pgnd phase dl2 lx2 dh2 dl1 lx1 dh1 v cc eaout ean diff en csp2 csn2 csp1 csn1 max5038 3 r1 c39 v in = +12v c1, c2 21 15 in c25 c26 r4 r7 r8 r6 c29 c30 r5 c27 c28 sgnd clp2 clp1 q2 q1 d2 q2 d1 v in q1 v in d4 d3 c32 c12 c31 c3?7 l2 r3 l1 r2 c13 c8?11 c14, c15 c16?24, c33 load +1.8v at 60a v out sense - sense + 17 18 19 16 20 25 24 23 26 9 8 14 13 1 2 bst1 v cc 28 4 10 11 12 7 5 6 22 bst2 note: see table 1 for component values. v cc r x figure 1. max5038 typical application circuit, v in = +12v
max5038/max5041 dual-phase, parallelable, average current-mode controllers 12 ______________________________________________________________________________________ dual-phase converters with an out-of-phase locking arrangement reduce the input and output capacitor ripple current, effectively multiplying the switching fre- quency by the number of phases. each phase of the max5038/max5041 consists of an inner average cur- rent loop controlled by a common outer-loop voltage- error amplifier (vea) that corrects the output voltage errors. the max5038/max5041 utilize a single control- ling vea and an average current mode to force the phase currents to be equal. clkin pllcmp pgnd phase dl2 lx2 dh2 dl1 lx1 dh1 v cc eaout ean diff en csp2 csn2 csp1 csn1 max5041 3 r1 c39 v in = +12v c1, c2 21 15 in c25 c26 r4 r7 r8 r6 c29 c30 r5 c27 c28 sgnd clp2 clp1 q2 q1 d2 q2 d1 v in q1 v in d4 d3 c32 c12 c31 c3?7 l2 r3 l1 r2 c13 c8?11 c14, c15 c16?24, c33 load +1.8v at 60a v out sense - sense + 17 18 19 16 20 25 24 23 26 9 8 14 13 1 2 bst1 v cc 28 4 10 11 12 7 5 6 22 bst2 note: see table 1 for component values. r h r l v cc r x figure 2. max5041 typical application circuit, v in = +12v
max5038/max5041 dual-phase, parallelable, average current-mode controllers ______________________________________________________________________________________ 13 v in and v cc the max5038/max5041 accept a wide input voltage range of +4.75v to +5.5v or +8v to +28v. all internal control circuitry operates from an internally regulated nominal voltage of +5v (v cc ). for input voltages of +8v or greater, the internal v cc regulator steps the voltage down to +5v. the v cc output voltage regulates to +5v while sourcing up to 80ma. bypass v cc to sgnd with 4.7? and 0.1? low-esr ceramic capacitors for high- frequency noise rejection and stable operation (figures 1 and 2). calculate power dissipation in the max5038/max5041 as a product of the input voltage and the total v cc reg- ulator output current (i cc ). i cc includes quiescent cur- rent (i q ) and gate drive current (i dd ): p d = v in x i cc i cc = i q + f sw x (q g1 + q g2 + q g3 + q g4 ) where, q g1 , q g2 , q g3, and q g4 are the total gate charge of the low-side and high-side external mosfets, i q is 4ma (typ), and f sw is the switching fre- quency of each individual phase. for applications utilizing a +5v input voltage, disable the v cc regulator by connecting in and v cc together. undervoltage lockout (uvlo)/ power-on reset (por)/soft-start the max5038/max5041 include an undervoltage lock- out with hysteresis and a power-on reset circuit for con- verter turn-on and monotonic rise of the output voltage. the uvlo threshold is internally set between +4.0v and +4.5v with a 200mv hysteresis. hysteresis at uvlo eliminates ?hattering?during startup. most of the internal circuitry, including the oscillator, turns on when the input voltage reaches +4v. the max5038/max5041 draw up to 4ma of current before the input voltage reaches the uvlo threshold. the compensation network at the current error ampli- fiers (clp1 and clp2) provides an inherent soft-start of the output voltage. it includes a parallel combination of capacitors (c28, c30) and resistors (r5, r6) in series with other capacitors (c27, c29) (see figures 1 and 2). the voltage at clp_ limits the maximum current avail- able to charge output capacitors. the capacitor on clp_ in conjunction with the finite output-drive current of the current-error amplifier yields a finite rise time for the output current and thus the output voltage. internal oscillator the internal oscillator generates the 180 out-of-phase clock signals required by the pulse-width modulation (pwm) circuits. the oscillator also generates the 2v p-p voltage ramp signals necessary for the pwm compara- tors. connect clkin to sgnd to set the internal oscillator frequency to 250khz or connect clkin to v cc to set the internal oscillator to 500khz. clkin is a cmos logic clock input for the phase- locked loop (pll). when driven externally, the internal oscillator locks to the signal at clkin. a rising edge at clkin starts the on cycle of the pwm. ensure that the external clock pulse width is at least 200ns. clkout provides a phase-shifted output with respect to the ris- ing edge of the signal at clkin. phase sets the amount of phase shift at clkout. connect phase to v cc for 120 of phase shift, leave phase unconnected for 90 of phase shift, or connect phase to sgnd for 60 of phase shift with respect to clkin. the max5038/max5041 require compensation on pllcmp even when operating from the internal oscillator. the device requires an active pll in order to generate the proper clock signal required for pwm operation. control loop the max5038/max5041 use an average current-mode control scheme to regulate the output voltage (figures 3a and 3b). the main control loop consists of an inner current loop and an outer voltage loop. the inner loop controls the output currents (i phase1 and i phase2 ) while the outer loop controls the output voltage. the inner current loop absorbs the inductor pole reducing the order of the outer voltage loop to that of a single- pole system. the current loop consists of a current-sense resistor (r s ), a current-sense amplifier (ca_), a current-error amplifier (cea_), an oscillator providing the carrier ramp, and a pwm comparator (cpwm_). the precision ca_ amplifies the sense voltage across r s by a factor of 18. the inverting input to the cea_ senses the ca_ output. the cea_ output is the difference between the voltage-error amplifier output (eaout) and the gained- up voltage from the ca_. the rc compensation net- work connected to clp1 and clp2 provides external frequency compensation for the respective cea_. the start of every clock cycle enables the high-side drivers and initiates a pwm on cycle. comparator cpwm_ compares the output voltage from the cea_ with a 0 to +2v ramp from the oscillator. the pwm on cycle termi- nates when the ramp voltage exceeds the error voltage. (1) (2)
max5038/max5041 dual-phase, parallelable, average current-mode controllers 14 ______________________________________________________________________________________ drive 2 drive 1 cpwm1 cpwm2 cea1 cea2 vea diff amp ca1 ca2 clp2 csp2 csn2 clp1 csn1 csp1 sense+ sense- v in v in load c out v out r in * r f * r s r s i phase1 i phase2 r cf c cff c cf r cf c ccf c cf max5041 v ref = +1.0v *r f and r in are external to max5041 (r f = r8, r in = r7, figure 2) figure 3b. max5041 control loop drive 2 drive 1 cpwm1 cpwm2 cea1 cea2 vea diff amp ca1 ca2 v ref c lp2 c sp2 c sn 2 c lp1 c sn 1 c sp1 sense+ sense- v in v in load c out v out r in * r f * r s r s i phase1 i phase2 r cf c cff c cf r cf c ccf c cf *r f and r in are external to max5038 (r f = r8, r in = r7, figure 1) max5038 figure 3a. max5038 control loop
max5038/max5041 dual-phase, parallelable, average current-mode controllers ______________________________________________________________________________________ 15 the outer voltage control loop consists of the differen- tial amplifier (diff amp), reference voltage, and vea. the unity-gain differential amplifier provides true differ- ential remote sensing of the output voltage. the differ- ential amplifier output connects to the inverting input (ean) of the vea. the noninverting input of the vea is internally connected to an internal precision reference voltage. the max5041 reference voltage is set to +1.0v and the max5038 reference is set to the preset output voltage. the vea controls the two inner current loops (figures 3a and 3b). use a resistive feedback network to set the vea gain as required by the adaptive volt- age-positioning circuit (see the adaptive voltage positioning section). current-sense amplifier the differential current-sense amplifier (ca_) provides a dc gain of 18. the maximum input offset voltage of the current-sense amplifier is 1mv and the common-mode voltage range is -0.3v to +3.6v. the current-sense ampli- fier senses the voltage across a current-sense resistor. peak-current comparator the peak-current comparator provides a path for fast cycle-by-cycle current limit during extreme fault condi- tions such as an output inductor malfunction (figure 4). note that the average current-limit threshold of 48mv still limits the output current during short-circuit condi- tions. to prevent inductor saturation, select an output inductor with a saturation current specification greater than the average current limit (48mv). proper inductor selection ensures that only extreme conditions trip the peak-current comparator, such as a cracked output inductor. the 112mv voltage threshold for triggering the peak-current limit is twice the full-scale average current-limit voltage threshold. the peak-current com- parator has a delay of only 260ns. current-error amplifier each phase of the max5038/max5041 has a dedicated transconductance current-error amplifier (cea_) with a typical g m of 550? and 320? output sink and source current capability. the current-error amplifier outputs, clp1 and clp2, serve as the inverting input to the pwm comparator. clp1 and clp2 are externally accessible to provide frequency compensation for the inner current loops (figures 3a and 3b). compensate cea_ such that the inductor current down slope, which becomes the up slope to the inverting input of the pwm comparator, is less than the slope of the internally gen- erated voltage ramp (see the compensation section). pwm comparator and r-s flip-flop the pwm comparator (cpwm) sets the duty cycle for each cycle by comparing the output of the current-error amplifier to a 2v p-p ramp. at the start of each clock cycle, an r-s flip-flop resets and the high-side driver (dh_) turns on. the comparator sets the flip-flop as soon as the ramp voltage exceeds the clp_ voltage, thus terminating the on cycle (figure 4). 2 x f s (v/s) ramp clk csp_ csn_ gm in shdn clp_ drv_v cc bst_ dh_ lx_ dl_ pgnd a v = 18 pwm comparator peak-current comparator 112mv s r q q g m = 500 s figure 4. phase circuit (phase 1/phase 2)
max5038/max5041 dual-phase, parallelable, average current-mode controllers 16 ______________________________________________________________________________________ differential amplifier the differential amplifier (diff amp) facilitates output voltage remote sensing at the load (figures 3a and 3b). it provides true differential output voltage sensing while rejecting the common-mode voltage errors due to high- current ground paths. sensing the output voltage directly at the load provides accurate load voltage sensing in high-current environments. the vea pro- vides the difference between the differential amplifier output (diff) and the desired output voltage. the dif- ferential amplifier has a bandwidth of 3mhz. the differ- ence between sense+ and sense- regulates to the preset output voltage for the max5038 and regulates to +1v for the max5041. voltage-error amplifier the vea sets the gain of the voltage control loop and determines the error between the differential amplifier output and the internal reference voltage (v ref ). v ref equals v out(nom) for the +1.8v or lower voltage versions of the max5038 and v ref equals v out(nom) /2 for the +2.5v and +3.3v versions. for max5041, v ref equals +1v. an offset is added to the output voltage of the max5038/max5041 with a finite gain (r f /r in ) of the vea such that the no-load output voltage is higher than the nominal value. choose r f and r in from the adaptive voltage positioning section and use the follow- ing equations to calculate the no-load output voltage. max5038: max5041: where r h and r l are the feedback resistor network (figure 2). some applications require v out equal to v out(nom) at no load. to ensure that the output voltage does not exceed the nominal output voltage (v out(nom) ), add a resistor r x from v cc to ean. use the following equations to calculate the value of r x . for max5038 versions of v out(nom) +1.8v: for max5038 versions of v out(nom) > +1.8v: for max5041: the vea output clamps to +0.9v (plus the common- mode voltage of +0.6v), thus limiting the average maxi- mum current from individual phases. the maximum average current-limit threshold for each phase is equal to the maximum clamp voltage of the vea divided by the gain (18) of the current-sense amplifier. this allows for accurate settings for the average maximum current for each phase. set the vea gain using r f and r in for the amount of output voltage positioning required as discussed in the adaptive voltage positioning section (figures 3a and 3b). adaptive voltage positioning powering new-generation processors requires new techniques to reduce cost, size, and power dissipation. voltage positioning reduces the total number of output capacitors to meet a given transient response require- ment. setting the no-load output voltage slightly higher than the output voltage during nominally loaded condi- tions allows a larger downward voltage excursion when the output current suddenly increases. regulating at a lower output voltage under a heavy load allows a larger upward-voltage excursion when the output current sud- denly decreases. a larger allowed, voltage-step excur- sion reduces the required number of output capacitors or allows for the use of higher esr capacitors. voltage positioning and the ability to operate with multiple reference voltages may require the output to regulate away from a center value. define the center value as the voltage where the output drops ( ? v out /2) at one half the maximum output current (figure 5). rv r v xcc f ref =? [.] 16 rvv r v x cc nom f nom =? + [( .)] 212 rv v r v x cc nom f nom =? + [( .)] 06 v r r rr r v out nl in f hl l ref () =+ ? ? ? ? ? ? + ? ? ? ? ? ? 1 v r r v out nl in f out nom () ( ) =+ ? ? ? ? ? ? 1 (3) (4) (5) (6) (7)
max5038/max5041 dual-phase, parallelable, average current-mode controllers ______________________________________________________________________________________ 17 set the voltage-positioning window ( ? v out ) using the resistive feedback of the vea. use the following equa- tions to calculate the voltage-positioning window for the max5038: use the following equation to calculate the voltage-posi- tioning window for the max5041: where r in and r f are the input and feedback resistors of the vea, g c is the current-loop gain and r s is the cur- rent-sense resistor or, if using lossless inductor current sensing, the dc resistance of the inductor. phase-locked loop: operation and compensation the pll synchronizes the internal oscillator to the external frequency source when driving clkin. connecting clkin to v cc or sgnd forces the pwm frequency to default to the internal oscillator frequency of 500khz or 250khz, respectively. the pll uses a conventional architecture consisting of a phase detec- tor and a charge pump capable of providing 20? of output current. connect an external series combination capacitor (c25) and resistor (r4) and a parallel capaci- tor (c26) from pllcmp to sgnd to provide frequency compensation for the pll (figure 1). the pole-zero pair compensation provides a zero at f z = 1 / [r4 x (c25 + c26)] and a pole at f p = 1 / (r4 x c26). use the follow- ing typical values for compensating the pll: r4 = 7.5k ? , c25 = 4.7nf, c26 = 470pf. if changing the pll frequency, expect a finite locking time of approxi- mately 200?. the max5038/max5041 require compensation on pllcmp even when operating from the internal oscilla- tor. the device requires an active pll in order to gen- erate the proper internal pwm clocks. mosfet gate drivers (dh_, dl_) the high-side (dh_) and low-side (dl_) drivers drive the gates of external n-channel mosfets (figures 1 and 2). the drivers?high-peak sink and source current capability provides ample drive for the fast rise and fall times of the switching mosfets. faster rise and fall times result in reduced cross-conduction losses. for modern cpu voltage-regulating module applications where the duty cycle is less than 50%, choose high- side mosfets (q1 and q3) with a moderate r ds(on) and a very low gate charge. choose low-side mosfets (q2 and q4) with very low r ds(on) and moderate gate charge. the driver block also includes a logic circuit that pro- vides an adaptive non-overlap time to prevent shoot- through currents during transition. the typical non-overlap time is 60ns between the high-side and low-side mosfets. bst_ v dd powers the low- and high-side mosfet drivers. connect a 0.47? low-esr ceramic capacitor between bst_ and lx_. bypass v cc to pgnd with 4.7? and 0.1? low-esr ceramic capacitors. reduce the pc board area formed by these capacitors, the rectifier diodes between v cc and the boost capacitor, the max5038/max5041, and the switching mosfets. g r c s = 005 . ? v ir gr rr r out out in cf hl l = () + 2 g r c s = 005 . ? v ir gr out out in cf = 2 load (a) v cntr no load 1/2 load full load voltage-positioning w indow v cntr + ? v out /2 v cntr - ? v out /2 figure 5. defining the voltage-positioning window (8) (9) (10) (11)
max5038/max5041 dual-phase, parallelable, average current-mode controllers 18 ______________________________________________________________________________________ overload conditions average current-mode control has the ability to limit the average current sourced by the converter during a fault condition. when a fault condition occurs, the vea out- put clamps to +0.9v with respect to the common-mode voltage (v cm = +0.6v) and is compared with the output of the current-sense amplifiers (ca1 and ca2) (see figures 3a and 3b). the current-sense amplifier? gain of 18 limits the maximum current in the inductor or sense resistor to i limit = 50mv/r s . parallel operation for applications requiring large output current, parallel up to three max5038/max5041s (six phases) to triple the available output current. the paralleled converters operate at the same switching frequency but different phases keep the capacitor ripple rms currents to a mini- mum. three parallel max5038/max5041 converters deliver up to 180a of output current. to set the phase shift of the on-board pll, leave phase unconnected for 90 of phase shift (2 paralleled converters), or connect phase to sgnd for 60 of phase shift (3 converters in parallel). designate one converter as master and the remaining converters as slaves. connect the master and slave controllers in a daisy-chain configuration as shown in figure 6. connect clkout from the master controller to clkin of the first slaved controller, and clkout from the first slaved controller to clkin of the second slaved controller. choose the appropriate phase shift for mini- mum ripple currents at the input and output capacitors. the master controller senses the output differential volt- age through sense+ and sense- and generates the diff voltage. disable the voltage sensing of the slaved controllers by leaving diff unconnected (floating). figure 7 shows a detailed typical parallel application cir- cuit using two max5038s. this circuit provides four phases at an input voltage of +12v and an output volt- age range of +1v to +3.3v at 104a. applications information each max5038/max5041 circuit drives two 180 out-of- phase channels. parallel two or three max5038/ max5041 circuits to achieve four- or six-phase opera- tion, respectively. figure 1 shows the typical application circuit for a two-phase operation. the design criteria for a two-phase converter includes frequency selection, inductor value, input/output capacitance, switching mosfets, sense resistors, and the compensation net- work. follow the same procedure for the four- and six- phase converter design, except for the input and output capacitance. the input and output capacitance require- ments vary depending on the operating duty cycle. the examples discussed in this data sheet pertain to a typical application with the following specifications: v in = +12v v out = +1.8v i out(max) = 52a f sw = 250khz peak-to-peak inductor current ( ? i l ) = 10a table 1 shows a list of recommended external compo- nents (figure 1) and table 2 provides component sup- plier information. number of phases selecting the number of phases for a voltage regulator depends mainly on the ratio of input-to-output voltage (operating duty cycle). optimum output-ripple cancella- tion depends on the right combination of operating duty cycle and the number of phases. use the following equation as a starting point to choose the number of phases: n ph k/d where k = 1, 2, or 3 and the duty cycle is d = v out /v in. choose k to make n ph an integer number. for exam- ple, converting v in = +12v to v out = +1.8v yields better ripple cancellation in the six-phase converter than in the four-phase converter. ensure that the output load justifies the greater number of components for multiphase conversion. generally limiting the maximum output current to 25a per phase yields the most cost- effective solution. the maximum ripple cancellation occurs when n ph = k/d. single-phase conversion requires greater size and power dissipation for external components such as the switch- ing mosfets and the inductor. multiphase conversion eliminates the heatsink by distributing the power dissipa- tion in the external components. the multiple phases operating at given phase shifts effectively increase the switching frequency seen by the input/output capacitors, thereby reducing the input/output capacitance require- ment for the same ripple performance. the lower induc- tance value improves the large-signal response of the converter during a transient load at the output. consider all these issues when determining the number of phases necessary for the voltage regulator application. inductor selection the switching frequency per phase, peak-to-peak rip- ple current in each phase, and allowable ripple at the output determine the inductance value. (12)
max5038/max5041 dual-phase, parallelable, average current-mode controllers ______________________________________________________________________________________ 19 clkin clkout sgnd pgnd in phase dl2 lx2 dh2 dl1 lx1 dh1 v cc v in eaout ean diff sense- sense+ csp2 csn2 csp1 csn1 v cc v in v in clkout sgnd pgnd in phase dl2 lx2 dh2 dl1 lx1 dh1 eaout ean clkin csp2 csn2 csp1 csn1 diff v cc v in v in clkout sgnd pgnd in phase dl2 lx2 dh2 dl1 lx1 dh1 eaout ean clkin csp2 csn2 csp1 csn1 diff v cc v in v in to other max5038/max5041s max5038/ max5041 max5038/ max5041 max5038/ max5041 load *for max5041 only. * * figure 6. parallel configuration of multiple max5038/max5041s
max5038/max5041 dual-phase, parallelable, average current-mode controllers 20 ______________________________________________________________________________________ max5038 (master) q4 q3 d2 q2 d1 v in 4 x 22 f c8?11 q1 v in v in = +12v v cc d4 d3 c40 0.1 f c12 0.47 f c38 4.7 f c3?7 5 x 22 f l2 0.6 h r2 1.35m ? l1 0.6 h r1 1.35m ? dh1 lx1 dl1 bst1 v cc dh2 lx2 dl2 bst2 csp2 csn2 pgood phase clkout sgnd pgnd clp2 clp1 r9 pgood v cc r6 c35 c36 r5 c33 c34 c39 0.1 f c1, c2 2 x 47 f r3 2.2 ? c31 c32 r4 csp1 csn1 sense+ sense- in clkin pllcmp r8 r7 eaout ean diff ovpin en c13 0.47 f c14, c15, c41, c42 2 x 100 f c16?25, c43?46 14 x 270 f c26?30, c37 6 x 10 f load v out = +1.1v to +3.3v at 104a v cc max5038 (slave) q8 q7 d6 q6 d5 v in c52?55 4 x 22 f q5 v in d8 d7 c64 0.1 f c57 0.47 f c65 4.7 f c48?51 5 x 22 f l4 0.6 h r11 1.35m ? l3 0.6 h r10 1.35m ? dh1 lx1 dl1 bst1 v cc dh2 lx2 dl2 bst2 csp2 csn2 phase sgnd pgnd clp2 clp1 v cc r15 c59 c58 r14 c60 c61 c47 0.1 f r12 2.2 ? c62 c63 r13 csp1 csn1 sense+ sense- clkin in pllcmp en r17 r16 eaout ean diff c56 0.47 f r18 r19 v cc r x v cc r x figure 7. four-phase parallel application circuit (v in = +12v, v out = +1.1v to +3.3v at 104a)
max5038/max5041 dual-phase, parallelable, average current-mode controllers ______________________________________________________________________________________ 21 table 1. component list designation qty description c1, c2 2 47?,16v x5r input-filter capacitors tdk c5750x5r1c476m c3?11 9 22?, 16v input-filter capacitors tdk c4532x5r1c226m c12, c13 2 0.47?, 16v capacitors tdk c1608x5r1a474k c14, c15 2 100?, 6.3v, output-filter capacitors murata grm44-1x5r107k6.3 c16?24, c33 10 270?, 2v output-filter capacitors panasonic eefue0d271r c25 1 4700pf, 16v x7r capacitor vishay-siliconix vj0603y471jxj c26, c28, c30 3 470pf 16v capacitors murata grm1885c1h471jab01 c27, c29 2 0.01? 50v x7r capacitors murata grm188r71h103ka01 c31 1 4.7? 16v x5r capacitor murata grm40-034x5r475k6.3 c32 3 0.1? 16v x7r capacitors murata grm188r71c104ka01 d1, d2 2 schottky diodes on-semiconductor mbrs340t3 d3, d4 2 schottky diodes on-semiconductor mbr0520lt1 l1, l2 2 0.6?, 27a inductors panasonic etqp1h0r6bfx q1, q3 2 upper-power mosfets vishay-siliconix si7860dp q2, q4 2 lower-power mosfets vishay-siliconix si7886dp r1 1 2.2 ? ?% resistor r2, r3 4 current-sense resistors, use two 2.7m ? resistors in parallel, panasonic erjm1wsf2m7u r4 1 7.5k ? ?% resistor r5, r6 2 1k ? ?% resistors r7 1 4.99k ? ?% resistor r8, r9 2 37.4k ? ?% resistors table 2. component suppliers supplier phone fax website murata 770-436-1300 770-436-3030 www.murata.com on semiconductor 602-244-6600 602-244-3345 www.on-semi.com panasonic 714-373-7939 714-373-7183 www.panasonic.com tdk 847-803-6100 847-390-4405 www.tcs.tdk.com vishay-siliconix 1-800-551-6933 619-474-8920 www.vishay.com
max5038/max5041 dual-phase, parallelable, average current-mode controllers 22 ______________________________________________________________________________________ selecting higher switching frequencies reduces the inductance requirement, but at the cost of lower efficien- cy. the charge/discharge cycle of the gate and drain capacitances in the switching mosfets create switching losses. the situation worsens at higher input voltages, since switching losses are proportional to the square of input voltage. use 500khz per phase for v in = +5v and 250khz or less per phase for v in > +12v. although lower switching frequencies per phase increase the peak-to-peak inductor ripple current ( ? i l ), the ripple cancellation in the multiphase topology reduces the input and output capacitor rms ripple current. use the following equation to determine the minimum inductance value: choose ? i l equal to about 40% of the output current per phase. since ? i l affects the output-ripple voltage, the inductance value may need minor adjustment after choosing the output capacitors for full-rated efficiency. choose inductors from the standard high-current, surface-mount inductor series available from various manufacturers. particular applications may require cus- tom-made inductors. use high-frequency core material for custom inductors. high ? i l causes large peak-to-peak flux excursion increasing the core losses at higher fre- quencies. the high-frequency operation coupled with high ? i l , reduces the required minimum inductance and even makes the use of planar inductors possible. the advantages of using planar magnetics include low- profile design, excellent current-sharing between phas- es due to the tight control of parasitics, and low cost. for example, calculate the minimum inductance at v in(max) = +13.2v, v out = +1.8v, ? i l = 10a, and f sw = 250khz: the average current-mode control feature of the max5038/max5041 limits the maximum peak inductor current which prevents the inductor from saturating. choose an inductor with a saturating current greater than the worst-case peak inductor current. use the following equation to determine the worst-case inductor current for each phase: where r sense is the sense resistor in each phase. switching mosfets when choosing a mosfet for voltage regulators, consider the total gate charge, r ds(on) , power dissipa- tion, and package thermal impedance. the product of the mosfet gate charge and on-resistance is a figure of merit, with a lower number signifying better performance. choose mosfets optimized for high-frequency switch- ing applications. the average gate-drive current from the max5038/ max5041 output is proportional to the total capacitance it drives from dh1, dh2, dl1, and dl2. the power dis- sipated in the max5038/max5041 is proportional to the input voltage and the average drive current. see the v in and v cc section to determine the maximum total gate charge allowed from all the driver outputs together. the gate charge and drain capacitance (cv 2) loss, the cross-conduction loss in the upper mosfet due to finite rise/fall time, and the i 2 r loss due to rms current in the mosfet r ds(on) account for the total losses in the mos- fet. estimate the power loss (pd mos _) in the high-side and low-side mosfets using following equations: where q g , r ds(on) , t r , and t f are the upper-switching mosfet? total gate charge, on-resistance at +25?, rise time, and fall time, respectively. where d = v out /v in , i dc = (i out - ? i l )/2 and i pk = (i out + ? i l )/2 iiiii d rms hi dc pk dc pk ? =++ () 22 3 pd q v f vi t t f ri mos hi g dd sw in out r f sw ds on rms hi ? ? = () + + () ? ? ? ? ? ? + 4 14 2 . () i r i l peak sense l _ . =+ 0 051 2 ? l k h min = ? () = 13 2 1 8 1 8 13 2 250 10 06 .. . . . l vvv vf i min inmax out out in sw l = ? () ? (13) (14) (15) (16) (17)
max5038/max5041 dual-phase, parallelable, average current-mode controllers ______________________________________________________________________________________ 23 for example, from the typical specifications in the applications information section with v out = +1.8v, the high-side and low-side mosfet rms currents are 9.9a and 24.1a, respectively. ensure that the thermal imped- ance of the mosfet package keeps the junction tem- perature at least 25? below the absolute maximum rating. use the following equation to calculate maxi- mum junction temperature: t j = pd mos x j-a + t a input capacitors the discontinuous input-current waveform of the buck converter causes large ripple currents in the input capacitor. the switching frequency, peak inductor cur- rent, and the allowable peak-to-peak voltage ripple reflected back to the source dictate the capacitance requirement. increasing the number of phases increas- es the effective switching frequency and lowers the peak-to-average current ratio, yielding lower input capacitance requirement. the input ripple is comprised of ? v q (caused by the capacitor discharge) and ? v esr (caused by the esr of the capacitor). use low-esr ceramic capacitors with high ripple-current capability at the input. assume the contributions from the esr and capacitor discharge are equal to 30% and 70%, respectively. calculate the input capacitance and esr required for a specified rip- ple using the following equation: where i out is the total output current of the multiphase converter and n is the number of phases. for example, at v out = +1.8v, the esr and input capacitance are calculated for the input peak-to-peak ripple of 100mv or less yielding an esr and capaci- tance value of 1m ? and 200?. output capacitors the worst-case peak-to-peak and capacitor rms ripple current, the allowable peak-to-peak output ripple volt- age, and the maximum deviation of the output voltage during step loads determine the capacitance and the esr requirements for the output capacitors. in multiphase converter design, the ripple currents from the individual phases cancel each other and lower the ripple current. the degree of ripple cancellation depends on the operating duty cycle and the number of phases. choose the right equation from table 3 to c alcu- late the peak-to-peak output ripple for a given duty cycle of two-, four-, and six-phase converters. the max- imum ripple cancellation occurs when n ph = k / d. c i n dd vf in out qsw = ? () 1 ? esr v i n i in esr out l = () + ? ? ? ? ? ? ? ? 2 iiiii d rms lo dc pk dc pk ? =++ () ? () 22 1 3 pd q v f cvf ri mos lo g dd sw oss in sw ds on rms lo ? ? = () + ? ? ? ? ? ? ? ? + 2 3 14 2 2 . () table 3. peak-to-peak output ripple current calculations number of phases (n) duty cycle (d) equation for ? i p-p 2 < 50% 2 > 50% 4 0 to 25% 4 25% to 50% 4 > 50% 6 < 17% ? i vd lf o sw = ? () 12 ? i vv d lf in o sw = ? () ? () 21 ? i vd lf o sw = ? () 14 ? i vdd dl f o sw = ?? ()() 12 4 1 2 ? i vd d dl f o sw = ?? ()( ) 2134 ? i vd lf o sw = ? () 16 (18) (19) (20) (21) (22)
max5038/max5041 dual-phase, parallelable, average current-mode controllers 24 ______________________________________________________________________________________ the allowable deviation of the output voltage during the fast transient load dictates the output capacitance and esr. the output capacitors supply the load step until the controller responds with a greater duty cycle. the response time (t response ) depends on the closed-loop bandwidth of the converter. the resistive drop across the capacitor esr and capacitor discharge causes a voltage drop during a step load. use a combination of sp polymer and ceramic capacitors for better transient load and ripple/noise performance. keep the maximum output voltage deviation less than or equal to the adaptive voltage-positioning window ( ? v out ). assume 50% contribution each from the out- put capacitance discharge and the esr drop. use the following equations to calculate the required esr and capacitance value: where i step is the load step and t response is the response time of the controller. controller response time depends on the control-loop bandwidth. current limit the average current-mode control technique of the max5038/max5041 accurately limits the maximum out- put current per phase. the max5038/max5041 sense the voltage across the sense resistor and limit the peak inductor current (i l-pk ) accordingly. the on cycle ter- minates when the current-sense voltage reaches 45mv (min). use the following equation to calculate maximum current-sense resistor value: where pd r is the power dissipation in sense resistors. select 5% lower value of r sense to compensate for any parasitics associated with the pc board. also, select a non-inductive resistor with the appropriate wattage rating. compensation the main control loop consists of an inner current loop and an outer voltage loop. the max5038/max5041 use an average current-mode control scheme to regulate the output voltage (figures 3a and 3b). i phase1 and i phase2 are the inner average current loops. the vea output provides the controlling voltage for these current sources. the inner current loop absorbs the inductor pole reducing the order of the outer voltage loop to that of a single-pole system. a resistive feedback around the vea provides the best possible response, since there are no capacitors to charge and discharge during large-signal excursions, r f and r in determine the vea gain. use the following equa- tion to calculate the value for r f : where g c is the current-loop gain and n is number of phases. when designing the current-control loop ensure that the inductor downslope (when it becomes an upslope at the cea output) does not exceed the ramp slope. this is a necessary condition to avoid sub-harmonic oscillations similar to those in peak current-mode control with insuffi- cient slope compensation. use the following equation to calculate the resistor r cf : for example, the maximum r cf is 12k ? for r sense = 1.35m ? . c cf provides a low-frequency pole while r cf provides a midband zero. place a zero at f z to obtain a phase bump at the crossover frequency. place a high-frequency pole (f p ) at least a decade away from the crossover frequency to achieve maximum phase margin. r fl vr cf sw out sense 210 2 g r c s = 005 . r ir ng v f out in c out = ? pd r r sense = ? 25 10 3 . r i n sense out = 0 045 . c it v out step response q = ? esr v i out esr step = ? (23) (24) (25) (26) (27) (28) (29)
max5038/max5041 dual-phase, parallelable, average current-mode controllers ______________________________________________________________________________________ 25 use the following equations to calculate c cf and c cff : pc board layout use the following guidelines to layout the switching voltage regulator. 1) place the v in and v cc bypass capacitors close to the max5038/max5041. 2) minimize the high-current loops from the input capacitor, upper switching mosfet, inductor, and output capacitor back to the input capacitor nega- tive terminal. 3) keep short the current loop from the lower switch- ing mosfet, inductor, and output capacitor and return to the source of the lower mosfet. 4) place the schottky diodes close to the lower mosfets and on the same side of the pc board. 5) keep the sgnd and pgnd isolated and connect them at one single point close to the negative termi- nal of the input filter capacitor. 6) run the current-sense lines cs+ and cs- very close to each other to minimize the loop area. similarly, run the remote voltage sense lines sense+ and sense- close to each other. do not cross these critical signal lines through power cir- cuitry. sense the current right at the pads of cur- rent-sense resistors. 7) avoid long traces between the v cc bypass capaci- tors, driver output of the max5038/max5041, mosfet gates and pgnd pin. minimize the loop formed by the v cc bypass capacitors, bootstrap diode, bootstrap capacitor, max5038/max5041, and upper mosfet gate. 8) place the bank of output capacitors close to the load. 9) distribute the power components evenly across the board for proper heat dissipation. 10) provide enough copper area at and around the switching mosfets, inductor, and sense resistors to aid in thermal dissipation. 11) use at least 4oz copper to keep the trace induc- tance and resistance to a minimum. thin copper pc boards can compromise efficiency since high cur- rents are involved in the application. also, thicker copper conducts heat more effectively, thereby reducing thermal impedance. chip information transistor count: 5431 process: bicmos c fr cff pcf = 1 2 c fr cf zcf = 1 2 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 clkin clkout bst2 dh2 lx2 dl2 en pgnd in v cc dl1 lx1 dh1 bst1 csn1 csp1 eaout ean diff sense- sense+ clp1 sgnd clp2 pllcmp phase csn2 csp2 ssop top view max5038a max5041a pin configuration (30) (31)
max5038/max5041 dual-phase, parallelable, average current-mode controllers maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 26 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2004 maxim integrated products printed usa is a registered trademark of maxim integrated products. ssop.eps package outline, ssop, 5.3 mm 1 1 21-0056 c rev. document control no. approval proprietary information title: notes: 1. d&e do not include mold flash. 2. mold flash or protrusions not to exceed .15 mm (.006"). 3. controlling dimension: millimeters. 4. meets jedec mo150. 5. leads to be coplanar within 0.10 mm. 7.90 h l 0 0.301 0.025 8 0.311 0.037 0 7.65 0.63 8 0.95 max 5.38 millimeters b c d e e a1 dim a see variations 0.0256 bsc 0.010 0.004 0.205 0.002 0.015 0.008 0.212 0.008 inches min max 0.078 0.65 bsc 0.25 0.09 5.20 0.05 0.38 0.20 0.21 min 1.73 1.99 millimeters 6.07 6.07 10.07 8.07 7.07 inches d d d d d 0.239 0.239 0.397 0.317 0.278 min 0.249 0.249 0.407 0.328 0.289 max min 6.33 6.33 10.33 8.33 7.33 14l 16l 28l 24l 20l max n a d e a1 l c h e n 1 2 b 0.068 package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .

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